This invention broadly relates to a power semiconductor circuit (hereinafter, may be referred to as a power IC), and in particular, to a power IC suitable for driving a load on the condition that a plurality of power ICs are connected in parallel.
When a load is driven by using a plurality of power ICs, the power IC often operates exceeding its rating in the cause of an over-load. If such a state continues for a long time, the power IC will be damaged.
To avoid such a damage, the power IC has been conventionally provided with an internal state sensor for detecting an internal state thereof. With this structure, the output of the internal state sensor is given to a microcomputer in order to control the power IC.
For example, when the power IC is put into an abnormal state, the internal state sensor detects this state. Under this circumstance, the microcomputer cuts off an input signal for the power IC on the basis of the output of the internal state sensor. Thereby, the drive of the power IC is halted such that the damage against the power IC is avoided in advance.
Thus, the control due to the variation of the internal state of the power IC has been carried out by the use of the microcomputer in the conventional power IC. Consequently, the control of the microcomputer becomes complex, and capacitance of a memory for storing a control program is inevitably increased. Further, a load for the microcomputer is increased also.
In consequence, when the load is driven in parallel by using a plurality of power ICs to enhance driving ability of the load, the respective internal states of the power ICs must be identified by the microcomputer.
Further, when the power ICs are controlled, respectively, the number of terminals connected to the microcomputer is more increased.
Herein, it is assumed that a plurality of power ICs are driven in parallel. When either one of the power ICs has an abnormality, the drive of the corresponding power IC is halted.
Simultaneously, the drives of the other power ICs must be halted so as to prevent the damages of the other power ICs. In the case where such a control is carried out by the use of the microcomputer, the load of the microcomputer is remarkably increased.
Alternatively, it is assumed that the power IC itself has a self-halting function. Under this circumstance, the abnormality takes place for the power IC, the drive of the power IC will be halted by the self-halting function.
When the power ICs are driven in parallel, the drive of the power IC having abnormality is immediately halted by the self-halting function. In this condition, an abnormal signal of the power IC is once supplied to the microcomputer, and the other ICs are controlled after the microcomputer carries out an internal process.
Consequently, variation of timing may totally occur for the control of the power ICs. As a result, it is difficult to synchronize a plurality of power ICs to each other in order to enhance apparent current driving ability.
It is therefore an object of this invention to provide a power IC which is capable of immediately halting a drive of a power IC without increasing a load of a microcomputer when the power IC has an abnormality.
It is another object of this invention to provide to a power IC in which a plurality of power ICs are synchronized so as to enhance apparent current driving ability when the power ICs are driven in parallel.
According to this invention, a power semiconductor circuit drives a load connected an output terminal. An output switch switches the output terminal to either one of an on-state and an off state. An internal state signal terminal produces an internal state of the circuit as a signal.
An internal state signal switch switches the internal state signal terminal to either one of an on-state and an off-state. An internal state sensor detects the internal state of the circuit.
A logic circuit is given with a control signal from an external control circuit, a detecting signal of the internal state sensor, and the signal from the internal state signal terminal, and switches the output switch and the internal state signal switch to either one of the on-state and the off-state on the basis of the given signals.
With such a structure, the internal state signal terminal may be connected to a resistor.
Under this circumstance, the internal state signal terminal is kept to a first potential level when the internal state signal switch is put into the off-state while the internal state signal terminal is kept to a second potential different from the first potential level when the internal state signal switch is put into the on-state. In this event, the second potential level may be equal to a ground level.
Further, the logic circuit switches the output switch to either one of the on-state and the off-state based upon change of the potential level of the internal state signal terminal.
Preferably, a drive circuit switches the output switch to either one of the on-state and the off-state in response to a signal from the logic circuit.
The external control circuit may be a microcomputer. In this case, the microcomputer is given with the signal from the internal state signal terminal, and an input signal of the logic circuit being changed based upon the signal from the internal state signal terminal.
Herein, the output switch or the internal state signal switch may be structured by a MOS transistor.
More specifically, when the abnormality takes place for the internal state, the output switch is switched, and the supply of the power for the load is halted. At the same time, the internal state signal switch is switched, and the level of the internal state signal terminal is changed.
Thereby, the abnormality is avoided in the power IC itself to prevent the damage. Further, the load of the process during the abnormal state of the microcomputer can be reduced.
Moreover, when one power IC has the abnormality with respect to the internal state, the operation of the corresponding power IC is halted. At the same time, the operation of another power IC is halted by the signal from the internal state signal terminal of the corresponding power IC.
Consequently, the damages of all power ICs can be prevented without increasing the load of the microcomputer. Further, the apparent current driving ability can be enhanced in synchronism with all power ICs.